RFM12B Bit Rates and Throughput

During the prototyping of the StrobIt Triggr, I found that I could only hit the maximum bit rate of approx 12000bps, this is a far cry from the reported 256Kbps, so what was I doing wrong?

It appears that there are a couple of factors that affect the data rate, one is how you connect to your Microcontroller and whether interrupt or polling is used.  There is also recommended MCU clock selections for different rates, which makes sense, as trying to handle high datarates on a 4MHZ MCU might be pushing things a bit too far.

Anyway here is a list of recommended MCU clock speeds and datarates that have been recommended (I have not tested these yet), also your result may vary if you use on chip hardware SPI rather than bitbanging SPI.

Clock Recommendations

kbps MHz
9.6 4
19.2 8
38.4 16
57.6 24
115.2 48

Update:  these are probably for PIC

Microcontroller Connections.

Another factor is how your MCU is connected to the RFM12B module and how you get the data from the RFM12B, this is a trade-off between speed and the amount of I/O pins.

  1. Minimal configuration.
  2. Non-Interrupt Based FIFO Usage.
  3. Speed Optimised FIFO Usage.

Minimal Configuration:

In this mode, only four microcontroller I/O ports are required to provide communication with the RFM12B.

The SDI, SCK and nSEL signals are used to configure the RFM12B. These pins are used to set the desired receive frequency, bandwidth, bit rate and so forth.

The SDO output with the nSEL=L is used (instead of the nIRQ) to indicate an active FIFO IT to the microcontroller.

LIMITATIONS:

  • When nSEL signal is logic high, the SDO output is in a high impedance state.
  • An SDO output logic level high signals that the number of the bits in the FIFO is greater than the set limit in the FIFO mode command.
  • The microcontroller is informed from the FIFO overflow, low battery condition or from an expired wake-up timer only when the status bits are read out.
  • (Alternatively, a fifth I/O connection (nIRQ pin) can be used to indicate the IT request.)
  • The FIFO content can be read out with the Status Read Command.

Non-Interrupt Based FIFO Usage.

The SDI, SCK and nSEL signals are used to configure the RFM12B.  These pins are used to set the desired receive frequency, bandwidth, bit rate and so forth.

The FFIT output is used (instead of the nIRQ) to indicate active FIFO IT to the microcontroller.
With the aid of the nFFSEL input, the FIFO can be directly accessed.

On each rising edge of the SCK input the FIFO content is rolled out on the SDO pin.

Speed Optimised FIFO Usage.

The SDI, SCK and nSEL signals are used to configure the RFM12B.  These pins are used to set the desired receive frequency, bandwidth, bitrate and so forth.

The FFIT output is used (instead of the nIRQ) to indicate active FIFO IT to the microcontroller.  With the aid of the nFFSEL input, the FIFO can be directly accessed.

On each rising edge of the SCK input the FIFO content is rolled out on the SDO pin.

The nIRQ connection can be optional, but if this line is omitted, the microcontroller can be informed from the FIFO overflow, low battery condition or from the expired wake-up timer only when the status bits are read out.

LIMITATION:

  • 2 further microcontroller pins are used (nFFS and FFIT)

UPDATED:

Some people have had some problems getting these working at high bitrates, one source of problem can be this Errata note

The clock output (Pin8) may generate high clock spurs in the RF output spectrum.

It is not recommended to use the clock output (Pin8). It can be disabled by setting the “dc” bit in the Power Management Command to (1). The next product revision is intended to solve the problem.

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Author: Stephen Eaton

Geek at heart. Loves to tinker and find out how things work, which inevitably leads to items in pieces and not working for much longer :)

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